Conventionally, a pedestal level clamping circuit in television receivers is constituted by a sample and hold circuit. A composite video signal is obtained by a tuning circuit of the television receiver. The pedestal level of the composite video signal is restored by the sample and hold circuit.
A typical example of a conventional sample and hold circuit used in a television receiver is shown in FIG. 1. For example, the conventional sample and hold circuit as shown in FIG. 1 has been used in a Toshiba IC device, model No. TA 7777.
As shown in FIG. 1, the sample and hold circuit is comprised of an input signal source 10, a differential circuit 12, a switch 14 and a capacitor 16.
In the differential circuit 12, a pair of first and second transistors 18 and 20 are coupled with each other in a differential manner. That is, the emitters of the first and second transistors 18 and 20 are coupled with each other.
A connection node 22 between the emitters of the transistors 18 and 20 is coupled to the switch 14. The switch 14 is coupled to a power supply source 24 through a constant current source 26. Further, a control terminal 14a of the switch 14 is coupled to a sampling pulse source 28.
The base of the first transistor 18 is coupled to a grounded terminal 30 through a series circuit of the input signal source 10 and a reference voltage source 32. The collector of the first transistor 18 is coupled to the grounded terminal 30 through a diode 34.
The base of the second transistor 20 is coupled to the grounded terminal 30 through the capacitor 16. Further, the base of the second transistor 20 is coupled to an output terminal 36. The collector of the second transistor 20 is coupled to the grounded terminal 30 through a third transistor 38. Further, the collector of the second transistor 20 is coupled to the capacitor 16.
The diode 34 and the third transistor 38 are coupled to each other so that a current mirror circuit 40 is formed.
The operation of the conventional sample and hold circuit shown, as in FIG. 1, will be briefly described.
The input signal source 10 provides an input signal, e.g., a composite video signal Sv. The composite video signal Sv is supplied to the base of the first transistor 10 together with a reference voltage Vref generated from the reference voltage source 32.
The sampling pulse source 28 provides a sampling pulse SP which varies periodically between the "H" or "1" level and the "L" or "0" level. In a television receiver, a burst gate pulse can be used as the sampling pulse SP. In this case, a burst gate pulse generator provided in a television receiver also is used as the sampling pulse source 28.
The sampling pulse SP controls the switch 14 so that the operation mode of the sample and hold circuit changes between a sampling mode and a holding mode, as described later.
When the switch 14 turns ON in response to the "H" level input of the sampling pulse SP, the sample and hold circuit enters into the sampling mode. In the sampling mode, the constant current source 26 supplies a prescribed constant current Ic to the differential circuit 12. Thus, the differential circuit 12 is activated.
The first transistor 18 receives at its base the composite video signal Sv and the reference voltage Vref. Then, a collector current I.sub.18 flows through the first transistor 18 in response to the composite video signal Sv biased by the reference voltage Vref. The current I.sub.18 flows through the diode 34 of the current mirror circuit 40. As a result, a mirror current I.sub.38, the same as the current I.sub.18, is obtained in the third transistor 38 due to the current mirror operation of the current mirror circuit 40.
The second transistor 20 receives at its base a current I.sub.16 which corresponds to a voltage V.sub.16 charged in the capacitor 16 at that time. Then, a collector current I.sub.20 flows through the second transistor 20 in response to the voltage V.sub.16.
The collectors of the second and third transistors 20 and 38 are connected to the capacitor 16. Thus, a current Id, i.e., the difference between the mirror current I.sub.38 flowing through the third transistor 38 and the collector current I.sub.20 flowing through the second transistor 20 flows into the capacitor 16 for charging the capacitor 16. The operations of the first and second transistors 18 and 20 balance with each other when the base potential of the second transistor 20, i.e., the voltage V.sub.16 charged to the capacitor 16, has reached the base potential of the first transistor 18. As a result, the capacitor 16 is charged to the voltage V.sub.16 equivalent to the composite video signal Sv biased by the reference voltage Vref.
When the switch 14 turns OFF, the sample and hold circuit enters into the holding mode. In the holding mode, the differential circuit 12 is disconnected from the constant current source 26 so that the differential circuit 12 is deactivated. In the deactivated condition of the differential circuit 12, the second and third transistors 20 and 38 connected to the capacitor 16 are also cut off. As a result, the charge of the capacitor 16 at the time when the switch 14 has turned OFF is held, without being discharged.
According to the above ON and OFF operations of the switch 14, a prescribed level of the composite video signal Sv is sampled by the differential circuit 12 and then held in the capacitor 16.
The conventional sample and hold circuit, as shown in FIG. 1, has a drawback as described below.
The pedestal level of the composite video signal Sv occasionally causes a sudden change. At that time, there arises a big gap between the base potentials of the first and second transistors 18 and 20. The first or second transistor 18 or 20 flows a large collector current I.sub.18 or I.sub.20 therethrough in response to the big potential gap. The collector current I.sub.18 or I.sub.20 is supplied from the constant current source 26, as described above.
Accordingly, the constant current Ic must be relatively large so that it can provide a sufficient amount for the collector current I.sub.18 or I.sub.20 in response to a maximum gap between the pedestal level of the composite video signal Sv and the charge voltage V.sub.16 applied to the bases of the first and second transistors 18 and 20, respectively.
Such a large amount of constant current Ic is supplied during the sampling mode, while the composite video signal Sv is almost stable so that such a sudden change of the pedestal level of the composite video signal Sv rarely occurs.
When S.sub.v is stable, which is in the largest percentage of time an excessive amount of the constant current Ic is wasted. In a typical example of a conventional television receiver, the constant current Ic would have a design value on the order of of hundreds to thousands of .mu.A. However, the actual amount of the collector current Ic is only dozens of .mu.A or less in most of the sampling periods.
As a result, a considerable amount of current is wasted in the conventional sample and hold circuit. Accordingly, it has been desired to reduce the constant current Ic of the sample and hold circuit. In a battery driven device, such as a portable television receiver, reduction of the constant current Ic has been eagerly sought.